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S3C6400X RISC MICROPROCESSOR
SD CLOCK STOP SEQUENCE
The flow chart for stopping the SD Clock is shown in Figure 27-4. The Host Driver does not stop the SD Clock
when a SD transaction takes place on the SD Bus -- namely, when either Command Inhibit (DAT) or Command
Inhibit (CMD) in the Present State register is set to 1.
(1)
Set SD Clock Enable in the Clock Control register to 0. Then, the Host Controller stops supplying the SD
Clock.
SD CLOCK FREQUENCY CHANGE SEQUENCE
The sequence for changing SD Clock frequency is shown in Figure 27-5. When SD Clock is still off, step (1) is
omitted.
(1)
Set SD Clock OFF
Figure 27-4. SD Clock Stop Sequence
(1)
SD Clock Stop
(2)
SD Clock Supply
Figure 27-5. SD Clock Change Sequence
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
START
Stop SD Clock
END
START
END
HSMMC CONTROLLER
27-5
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