Samsung S3C6400X User Manual page 830

S3C6400X RISC MICROPROCESSOR
AHBIdle
DMAReq
[29:11]
TxFNum
TxFFlsh
RxFFlsh
INTknQFlsh
FrmCntrRst
[31] RO AHB Master Idle
Indicates that the AHB Master State Machine is in
the IDLE condition.
[30] RO DMA Request Signal
Indicates that the DMA request is in progress. Used
for debug.
Reserved
[10:6] R_W TxFIFO Number
This is the FIFO number that must be flushed using
the TxFIFO Flush bit. This field must not be changed
until the core clears the TxFIFO Flush bit.
· 5'h0 : Non-Periodic TxFIFO flush
5'h1 : Periodic TxFIFO 1 flush in Device mode for
Periodic TxFIFO flush in Host mode
· 5'h2 : Periodic TxFIFO 2 flush in Device mode
···
· 5'hF : Periodic TxFIFO 15 flush in Device mode
· 5'h10 : Flush all the Periodic and Non-Periodic
TxFIFOs in the core
[5] R_WS_ TxFIFO Flush
SC
This bit selectively flushes a single or all transmit
FIFOs, but cannot do so if the core is in the midst of
a transaction. The application must only write this bit
after checking that the core is neither writing to the
TxFIFO nor reading from the TxFIFO. The
application must wait until the core clears this bit
before performing any operations. This bit takes 8
clocks to clear.
[4] R_WS_ RxFIFO Flush
SC
The application can flush the entire RxFIFO using
this bit, but must first ensure that the core is not in
the middle of a transaction. The application must
only write to this bit after checking that the core is
neither reading from the RxFIFO nor writing to the
RxFIFO. The application must wait until the bit is
cleared before performing any other operations. This
bit will take 8 clocks to clear.
[3] R_WS_ IN Token Sequence Learning Queue Flush
SC
The application writes this bit to flush the IN Token
Sequence Learning Queue.
[2] R_WS_ Host Frame Counter Reset
SC
The application writes this bit to reset the (micro)
frame number counter inside the core. When the
(micro)frame counter is reset, the subsequent SOF
sent out by the core will have a (micro)frame number
of 0.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
USB2.0 HS OTG
1'b1
1'b1
19'h0
5'h0
·
1'b0
1'b0
1'b0
1'b0
26-23