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S3C6400 RISC MICROPROCESSOR
DESCRIPTION
The following sections describe the UART operations that include data transmission, data reception, interrupt
generation, baud-rate generation, Loopback mode, Infra-red mode, and auto flow control.
DATA TRANSMISSION
The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit
and 1 to 2 stop bits, which can be specified by the line control register (ULCONn). The transmitter can also
produce the break condition, which forces the serial output to logic 0 state for one frame transmission time. This
block transmits break signals after the present transmission word is transmitted completely. After the break
signal transmission, it continuously transmits data into the Tx FIFO (Tx holding register in the case of Non-FIFO
mode).
DATA RECEPTION
Like the transmission, the data frame for reception is also programmable. It consists of a start bit, 5 to 8 data
bits, an optional parity bit and 1 to 2 stop bits in the line control register (ULCONn). The receiver can detect
overrun error, parity error, frame error and break condition, each of which can set an error flag.
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The overrun error indicates that new data has overwritten the old data before the old data has been read.
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The parity error indicates that the receiver has detected an unexpected parity condition.
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The frame error indicates that the received data does not have a valid stop bit.
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The break condition indicates that the RxDn input is held in the logic 0 state for a duration longer than
one frame transmission time.
Receive time-out condition occurs when it does not receive any data during the 3 word time (this interval follows
the setting of Word Length bit) and the Rx FIFO is not empty in the FIFO mode.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
UART
31-3
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