Samsung S3C6400X User Manual page 849

USB2.0 HS OTG
HOST CHANNEL-SPECIFIC REGISTERS
HOST CHANNEL-n CHARACTERISTICS REGISTER (HCCHARn)
Channel_number: 0≤ n≤ 15
Register Address
HCCHARn 0x7C00_0500
+n*20h
HCCHARn
ChEna
ChDis
OddFrm
DevAddr [28:22]
MC/EC [21:20]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-42
Specifications and information herein are subject to change without notice.
R/W
R/W
Bit R/W
[31] R_WS_ Channel Enable
SC This field is set by the application and cleared by the
OTG host.
· 1'b0 : Channel disabled
· 1'b1 : Channel enabled
[30] R_WS_ Channel Disable
SC
The application sets this bit to stop
transmitting/receiving data on a channel, even
before the transfer for that channel is complete. The
application must wait for the Channel Disabled
interrupt before treating the channel as disabled.
[29] R_W Odd Frame
This field is set (reset) by the application to indicate
that the OTG host must perform a transfer in an odd
(micro)frame. This field is applicable for only periodic
transactions.
· 1'b0 : Even (micro)frame
· 1'b1 : Odd (micro)frame
R_W Device Address
This field selects the specific device serving as the
data source or sink.
R_W Multi Count/Error Count
When the Split Enable bit of the Host Channel-n Split
Control register is reset (1'b0), this field indicates to
the host the number of transactions that must be
executed per microframe for this endpoint.
· 2'b00 : Reserved
· 2'b01 : 1 transaction
· 2'b10 : 2 transactions to be issued for this endpoint
per microframe
· 2'b11 : 3 transactions to be issued for this endpoint
per microframe
When HCSPLTn.SpltEna is set, this field indicates
the number of immediate retries to be performed for
a periodic split transactions on transaction errors.
Description
Host Channel-n Characteristics Register
Description
S3C6400X RISC MICROPROCESSOR
Reset Value
Initial State
32 bits
1'b0
1'b0
1'b0
7'h0
2'b0