Samsung S3C6400X User Manual page 812

S3C6400X RISC MICROPROCESSOR
OTG LINK CSR MEMORY MAP
Figure 26-2 shows the OTG link CSR address map. Host and Device mode registers occupy different addresses.
All registers are implemented in the AHB Clock domain.
OTG LINK BASE + 0000h
OTG LINK BASE + 0400h
OTG LINK BASE + 0800h
OTG LINK BASE + 0E00h
OTG LINK BASE + 1000h
OTG LINK BASE + 2000h
OTG LINK BASE + 3000h
OTG LINK BASE + F000h
OTG LINK BASE + 10000h
Device EP 0/Host Channel 0 FIFO (4 KB)
Device EP 1/Host Channel 1 FIFO (4 KB)
Device EP 14/Host Channel 14 FIFO (4 KB)
Device EP 15/Host Channel 15 FIFO (4 KB)
Figure 26-2. OTG Link CSR Memory Map
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Core Global CSRs (1 KB)
Host Mode CSRs (1 KB)
Device Mode CSRs (1.5 KB)
Reserved
●
●
●
USB2.0 HS OTG
26-5