Samsung S3C6400X User Manual page 109

S3C6400X RISC MICROPROCESSOR
SDRAM MEMORY INTERFACE
DRAM Controller supports up to two chips of same type and can assign a maximum of 256 MByte address space
per chip. All chips in the same port share all pins, except clock enable signals and chip select signals. An example
of DDR SDRAM memory interface connection is shown in figure 5-2. Mobile DDR SDRAM can be connected
similar to the DDR SDRAM. SDR SDRAM and mobile SDR SDRAM are connected similar to DDR
except that DQS pins are not connected. External Memory Pin configuration is as shown in table 5-1 and 5-2.
Reset value of CKE is controlled by SPCONSLP[4]. If the value is zero, Xm0CKE and Xm1CKE are zero when
reset. If the value is one, Xm0CKE and Xm1CKE are one when reset.
Signal
Xm0SCLK
Xm0SCLKn
Xm0CKE
Xm0CSn[6:7]
Xm0RAS
Xm0CAS
Xm0WEndmc
Xm0ADDR[13:0]
Xm0ADDR[15:14]
Xm0DATA[15:0]
Xm0DQM[1:0]
Xm0DQS[1:0]
Signal
Xm1SCLK
Xm1SCLKn
Xm1CKE[1:0]
Xm1CSN[1:0]
Xm1RAS
Xm1CAS
Xm1WEN
Xm1ADDR[13:0]
Xm1ADDR[15:14]
Xm1DATA[31:0]
Xm1DQM[3:0]
Xm1DQS[3:0]
Table 5-1 Memory Port 0 Pin Description
Type Description
Input Memory clock
Input Memory clock (negative)
Input Clock enable per chip
Input Chip select per chip (active low)
Input Row address strobe (active low)
Input Column address strobe (active low)
Input Write enable (active low)
Input Address bus
Input Bank select
Inout Data bus
Input Data bus mask bits
Inout Data strobe inout, DDR and mDDR only
Table 5-2 Memory Port 1 Pin Description
Type Description
Input Memory clock
Input Memory clock (negative)
Input Clock enable per chip
Input Chip select per chip (active low)
Input Row address strobe (active low)
Input Column address strobe (active low)
Input Write enable (active low)
Input Address bus
Input Bank select
Inout Data bus
Input Data bus mask bits
Inout Data strobe inout, DDR and mDDR only
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
DRAM CONTROLLER
SDRAM,
5-3