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S3C6400X RISC MICROPROCESSOR
MFCCLK_SEL
RESERVED
EPLL_SEL
MPLL_SEL
APLL_SEL
[4]
Control MUXMFC, which is the source clock of MFC
[3]
RESERVED
[2]
Control MUX
EPLL
[1]
Control MUX
MPLL
[0]
Control MUX
APLL
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
(0:FIN
, 1:FOUT
)
EPLL
EPLL
(0:FIN
, 1:FOUT
)
MPLL
MPLL
(0:FIN
, 1:FOUT
)
APLL
APLL
SYSTEM CONTROLLER
0
0
0
0
0
3-25
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