Samsung S3C6400X User Manual page 498

S3C6400X RISC MICROPROCESSOR
Next Frame DMA End Address Register for Output Cb and Cr
Register
NxtADDREnd_oCb
Register
NxtADDREnd_oCr
POSTENVID Register for Enable Video Processing
Register Address
POSTENVID 0x7630009C
Address R/W
0x76300094 R/W
Address R/W
0x76300098 R/W
R/W Bit
Enable Video Processing. It turns on the operation of
TV Scaler. It is de-asserted automatically after
operation of the current frame is finished. It should
R/W [31] be disabled (POSTENVID=0) during control register
configuration state. It can not be de-asserted during
operation. But it can be de-asserted in case that TV
Scaler is only ready for operation.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Bit Description
Next Frame DMA (Buffer 1) End
address for destination Cb component
[30:0]
(For more information refer to chapter
16-4)
Bit Description
Next Frame DMA (Buffer 1) End
address for destination Cr component
[30:0]
(For more information refer to chapter
16-4)
Description
TV SCALER
Reset Value
0x20006300
Reset Value
0x20006300
Reset Value
0x0
16-31