Samsung S3C6400X User Manual page 828

S3C6400X RISC MICROPROCESSOR
NPTxFEmpLvl
DMAEn
HBstLen
GlblIntrMsk
OTG USB CONFIGURATION REGISTER (GUSBCFG)
This register can be used to configure the core after power-on or a changing to Host mode or Device mode. It
contains USB and USB-PHY related configuration parameters. The application must program this register before
starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial
programming.
Register Address
GUSBCFG 0x7C00_000
C
the Periodic TxFIFO is half empty
· 1'b1 : GINTSTS.PTxFEmp interrupt indicates that
the Periodic TxFIFO is completely empty
[7] R_W Non-Periodic TxFIFO Empty Level
Indicates when the Non-Periodic TxFIFO Empty
Interrupt bit in the Core Interrupt register
(GINSTS.NPTxFEmp) is triggered. This bit is used
only in Slave mode.
· 1'b0 : GINTSTS.NPTxFEmp interrupt indicates that
the Non-Periodic TxFIFO is half empty
· 1'b1 : GINTSTS.NPTxFEmp interrupt indicates that
the Non Periodic TxFIFO is completely empty
[6] Reserved
[5] R_W DMA Enable
· 1'b0 : Core operates in Slave mode
· 1'b1 : Core operates in a DMA mode
[4:1] R_W Burst Length/Type
Internal DMA Mode – AHB Master burst type :
· 4'b0000 : Single
· 4'b0001 : INCR
· 4'b0011 : INCR4
· 4'b0101 : INCR8
· 4'b0111 : INCR16
· Others : Reserved
[0] R_W Global Interrupt Mask
The application uses this bit to mask or unmask the
interrupt line assertion to itself.
· 1'b0 : Mask the interrupt assertion to the
application
· 1'b1 : Unmask the interrupt assertion to the
application
R/W
R/W
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Core USB Configuration Register
USB2.0 HS OTG
1'b0
1'b0
1'b0
4'b0
1'b0
Reset Value
32 bits
26-21