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S3C6400X RISC MICROPROCESSOR
9. You must read JPGIRQ and JPGSTS registers to clear internal pended IRQs.
JPEG DECODING SEQUENCE: HARDWARE CONTROLLED DECODING (ONLY 1 FRAME)
Figure 22-6. Example flow chart of hardware controlled decoding
Take the following steps for hardware controlled JPEG decoding:
1.
Set the process mode to decoding process in JPGMOD.
2.
Set the destination address of 1st decoded image data IMG_ADDR0 and 2nd decoded image data
address IMG_ADDR1.
3.
Set the source address of 1st JPEG file HUFADDR0 and next JPEG file Address HUFADDR1.
4.
Set the HW_DEC to 1 in JPGCON
HW_DEC, CLK_SEL
1
5.
Set the Miscellaneous register MISC (set MODE_SEL to 0x1 or 0x2 , DMS bit to 0).
6.
Set the SW_JSTART to high.
7.
If MAIN_IRQ is high and ERR_IRQ is low, read frame size (in byte) from JPGCNT register.
8.
You must read JPGIRQ and JPGSTS registers to clear internal pended IRQs.
Start
Decoding proc.
Set JPGMOD
Set
IMG_ADDRx
Set
HUF_ADDRx
Set
JPGCON
Set
MISC
Set
SW_JSTART
N
MAIN_IRQ
is high ?
0
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Y
Decoding
Y
more frame?
N
Encoding proc.
Finished
JPEG CODEC
22-9
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