Samsung S3C6400X User Manual page 121

S3C6400X RISC MICROPROCESSOR
Pn_id_<n>_cfg Bit
[31:10]
QoS_MAX [9:2]
QoS_MIN [1]
QoS_Enable [0]
CHIP_N_CFG REGISTER
Register
P0_chip_0_cfg 0x7E000200
P0_chip_1_cfg 0x7E000204
P1_chip_0_cfg 0x7E001200
P1_chip_1_cfg 0x7E001204
Pn_chip_<n>_cfg
BRC_RBC
Address match
Address mask
USER_STATUS REGISTER
Register
P0_user_stat 0x7E000300
P1_user_stat 0x7E001300
Pn_user_stat
DQS[3] delay
DQS[2] delay
DQS[1] delay
DQS[0] delay
Read undefined. Write as Zero
Set a maximum quality of service.
Set a minimum quality of service.
Enables a quality of service value to be applied to memory reads
from address ID <n>.
Address R/W
R/W
R/W
Bit
[31:17] Read undefined. Write as Zero
Selects the memory organization as decoded from the AXI
address:
[16]
0 = Row-Bank-Column organization.
1 = Bank-Row-Column organization.
Comparison value for AXI address bits [31:24] to determine
[15:8]
which chip is selected.
The mask for AXI address bits [31:24] to determine which
chip is selected:
[7:0]
1 = corresponding address bit is to be used for comparison
Address R/W
R
R
Bit
[31:8] Read undefined. Write as Zero
[7:6] Shows input dqs[3] delay.
[5:4] Shows input dqs[2] delay.
[3:2] Shows input dqs[1] delay.
Shows input dqs[0] delay.
[1:0]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
16-bit DRAM controller chip_<n>_cfg register
32-bit DRAM controller chip_<n>_cfg register
Description
Description
16-bit DRAM controller user_stat register
32-bit DRAM controller user_stat register
Description
DRAM CONTROLLER
Initial State
0x00
0
0
Reset Value
0x0FF00
0x0FF00
Initial State
0
0xFF
0x00
Reset Value
0x00
0x00
Initial State
0
0
0
0
5-15