Samsung S3C6400X User Manual page 108

DRAM CONTROLLER
Supports 2 outstanding exclusive access transfers.
Configurable memory access timing by using SFRs.
Support extended MRS (EMRS) set.
For Memory Port 1, CKE can be controlled separately.
For Memory Port 1, Not supports 16bit SDR SDRAM, mobile SDR SDRAM
BLOCK DIAGRAM
Following figure 5-1 shows the block diagram of PL340 DRAM Controller
AXI domain
Read address
channel
Write address
channel
Buffered write
response channel
channel
channel
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
5-2
Specifications and information herein are subject to change without notice.
AXI low-power
interface channel
Memory
manager
AXI
slave
interface
Write
Read
Figure 5-1 DRAM Controller Block Diagram
AMBA 3.0 APB
interface
APB
slave
interface
Arbiter
Memory
interface
Read data
S3C6400X RISC MICROPROCESSOR
APB domain
Memory
domain
External
Pad memory
interface interface
to SDRAM