Samsung S3C6400X User Manual page 186

S3C6400X RISC MICROPROCESSOR
MAIN DATA AREA ECC0 STATUS REGISTER
Register Address
NFMECC0 0x70200034
NFMECC1 0x70200038
When ECCType is SLC
NFMECC0
MECC0_3
MECC0_2
MECC0_1
MECC0_0
NFMECC1
Reserved
Note: The NAND flash controller generate NFMECC when read or write main area data while the MainECCLock
(NFCONT[7]) bit is '0'(Unlock).
When ECCType is MLC.
NFMECC0 Bit
th
4 Parity [31:24]
rd
3 Parity [23:16]
nd
2 Parity [15:8]
st
1 Parity [7:0]
NFMECC1 Bit
Reserved [31:24]
th
7 Parity [23:16]
th
6 Parity [15:8]
th
5 Parity [7:0]
Note: The NAND flash controller generate these ECC parity codes when write main area data while the
MainECCLock (NFCON[7]) bit is '0' (unlock).
R/W
R SLC or MLC NAND Flash ECC status register
R MLC NAND Flash ECC status register
Bit
[31:24] ECC3 for data[7:0]
[23:16] ECC2 for data[7:0]
[15:8] ECC1 for data[7:0]
[7:0] ECC0 for data[7:0]
Bit
[31:0] Reserved
th
4 Check Parity generated from main area (512-byte)
rd
3 Check Parity generated from main area (512-byte)
nd
2 Check Parity generated from main area (512-byte)
st
1 Check Parity generated from main area (512-byte)
Reserved
th
7 Check Parity generated from main area (512-byte)
th
6 Check Parity generated from main area (512-byte)
th
5 Check Parity generated from main area (512-byte)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
Description
Description
Description
NAND FLASH CONTROLLER
Reset Value
0xXXXXXX
0xXXXXXX
Initial State
0xXX
0xXX
0xXX
0xXX
Initial State
0x00000000
Initial State
0x00
0x00
0x00
0x00
Initial State
0x00
0x00
0x00
0x00
8-25