Samsung S3C6400X User Manual page 932

HSMMC CONTROLLER
NORMAL INTERRUPT SIGNAL ENABLE REGISTER
This register is used to select which interrupt status is indicated to the Host System as the interrupt. These status
bits all share the same1 bit interrupt line. To enable interrupt generate set any of this bit to 1.
Register
NORINTSIGEN0 0x7C200038
NORINTSIGEN1 0x7C300038
NORINTSIGEN2 0x7C400038
Name Bit
[15]
EnSigFIA3 [14]
EnSigFIA2 [13]
EnSigFIA1 [12]
EnSigFIA0 [11]
EnSigRWait [10]
EnSigCCS [9]
[8]
[7]
[6]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
27-56
Specifications and information herein are subject to change without notice.
Address R/W
R/W
R/W
R/W
Fixed to 0
The Host Driver shall control error interrupts using the Error Interrupt
Signal Enable register.
FIFO SD Address Pointer Interrupt 3 Signal Enable
'1' = Enabled
'0' = Masked
FIFO SD Address Pointer Interrupt 2 Signal Enable
'1' = Enabled
'0' = Masked
FIFO SD Address Pointer Interrupt 1 Signal Enable
'1' = Enabled
'0' = Masked
FIFO SD Address Pointer Interrupt 0 Signal Enable
'1' = Enabled
'0' = Masked
Read Wait Interrupt Signal Enable
'1' = Enabled
'0' = Masked
CCS Interrupt Signal Enable
Command Complete Singal Interrupt Status bit is for CE-ATA interface
mode.
'1' = Enabled
'0' = Masked
Card Interrupt Signal Enable
'1' = Enabled
'0' = Masked
Card Removal Signal Enable
'1' = Enabled
'0' = Masked
Card Insertion Signal Enable
'1' = Enabled
'0' = Masked
Description
Normal Interrupt Signal Enable Register
(Channel 0)
Normal Interrupt Signal Enable Register
(Channel 1)
Normal Interrupt Signal Enable Register
(Channel 2)
Description
S3C6400X RISC MICROPROCESSOR
Reset Value
Initial Value
0x0
0x0
0x0
0
0
0
0
0
0
0
0
0
0