Ata_Control - Samsung S3C6400X User Manual

S3C6400X RISC MICROPROCESSOR

ATA_CONTROL

Register
ATA_CONTROL 0x70301900
ATA_CONTROL
Reserved
CLK_DOWN_READY
ATA_ENABLE
ATA_STATUS
Register
ATA_STATUS 0x70301904
ATA_STATUS
Reserved
ATADEV_IRQ
ATADEV_IORDY
ATADEV_DMAREQ
XFR_STATE
Address
ATA enable and clock down status
Bits
[31:2] Reserved bits
[1] Status for clock down
This bit is asserted in idle state when
ATA_CONTROL bit [0] is zero.
0 : not ready for clock down
1 : ready for clock down
[0] ATA enable
0 : ATA is disabled and preparation for clock
down maybe in progress
1 : ATA is enabled.
When this value is set to 1, delay of 200ms will
be required.
Address
Bits
[31:5] Reserved bits
[4] ATAPI interrupt signal line
[3] ATAPI iordy signal line
[2] ATAPI dmareq signal line
[1:0] Transfer state
2'b00 : idle state
2'b01 : transfer state
2'b11 : wait for completion state
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
Description
ATA controller status
Description
CF CONTROLLER
Reset Value
0x0000_0002
R/W Reset Value
R 0x0
R 0x1
R/W 0x0
Reset Value
0x0000_0000
R/W Reset Value
R 0x0
R 0x0
R 0x0
R 0x0
R 0x0
9-21