Samsung S3C6400X User Manual page 60

S3C6400X RISC MICROPROCESSOR
Figure 3-17. Power domains at SLEEP mode (only ALIVE and RTC keep internal state)
The following are the SLEEP mode entering sequence:
1. User software sets PWR_CFG[6:5] as SLEEP mode
2. User software generates STANDBYWFI signal by MCR instruction (MCR p15, 0, Rd, c7, c0, 4)
3. SYSCON requests bus controller to finish current AHB bus transaction
4. AHB bus controller sends acknowledge to SYSCON after current bus transaction is completed.
5. SYSCON requests DOMAIN-V to finish current AXI-bus transaction.
6. AXI bus controller sends acknowledge to SYSCON after current bus transaction is completed.
7. SYSCON requests external memory controllers to enter into self-refresh mode, since the contents in the
external memory must be preserved during SLEEP mode.
8. The memory controllers send acknowledges when they are self-refresh mode.
9. SYSCON changes clock source from PLL output to external oscillator if PLL is used.
10. SYSCON disables PLL operations and crystal oscillator.
11. Finally, SYSCON disables an external power source for internal logic by asserting XPWRRGTON pin to low
state. XPWRRGTON signal controls an external regulator.
The following are the SLEEP mode exiting sequence:
1. SYSCON enables an external power source by asserting XPWRRGTON pin to high state and waits for the
stable time, which is configured by PWR_STABLE.
2. SYSCON generates system clocks including HCLK, PCLK, and ARMCLK.
3. SYSCON releases system reset signals including HRESETn and PRESETn.
4. NFCON copies boot code from an external NAND device to the stepping stone if the boot device is NAND.
(XOM[4:3] == 2'b00)
5. SYSCON releases ARM reset signals.
DOMAIN DOMAIN
V I
DOMAIN
X
ARM11
PERIPHERAL
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
DOMAIN DOMAIN
MEMSYS
P F
AXI (64b)
DOMAIN DOMAIN DOMAIN
T M
AXI (32b)
APB (32b)
SYSTEM CONTROLLER
S
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