Samsung S3C6400X User Manual page 377

S3C6400X RISC MICROPROCESSOR
4BPP display(Palette)
(BSWP = 0, HWSWP = 0)
D[31:28]
000H P1
004H P9
008H P17
...
(BSWP = 1, HWSWP = 0)
D[31:28] D[27:24] D[23:20] D[19:16] D[15:12]
000H P7
004H P15
008H P23
...
Note:
1. AEN : Transparency value selection bit
AEN = 0 : Select ALPHA0
AEN = 1 : Select ALPHA1
If per-pixel blending is set, then this pixel would be blended with alpha value selected by AEN.
Alpha value is selected by SFR value as ALPHA0_R, ALPHA0_G, ALPHA0_B, ALPHA1_R, ALPHA1_G,
ALPHA1_B. For more information refer to description of SFR.
D[27:24] D[23:20] D[19:16]
P2 P3
P10 P11
P18 P19
P8 P5
P16 P13
P24 P21
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
D[15:12] D[11:8]
P4 P5 P6
P12 P13 P14
P20 P21 P22
D[11:8]
P6 P3 P4
P14 P11 P12
P22 P19 P20
DISPLAY CONTROLLER
D[7:4] D[3:0]
P7 P8
P15 P16
P23 P24
D[7:4] D[3:0]
P1 P2
P9 P10
P17 P18
14-15