Samsung S3C6400X User Manual page 967

S3C6400X RISC MICROPROCESSOR
SWRST_REG
SWRST_REG is software reset.
Address = BASEADDR + 0x14
Bits Name
[31:1] Reserved
[0] Sw_rst
CHID_REG
CHID_REG is channel ID RxFIFO output.
Address = BASEADDR + 0x18
Bits Name
[31:3] Reserved
[2:0] CURR_ID
Note: Channel ID is read once when Data is written in FIFO again after FIFO become empty, because Data in Rx
Data FIFO have the same channel ID.
DATA_REG
DATA_REG is RxFIFO output.
Address = BASEADDR + 0x1C
Bits Name
[31:0] RxFIFO out
Description
Reserved bits
Software reset
0 : set
Table 28-18 SWRST_REG register description
Description
Reserved bits
Current Channel ID
Table 28-19 CHID_REG register description
Description
RxFIFO data output
Table 28-20 DATA_REG register description
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1 : reset
MIPI HSI
R/W Reset Value
R 0x00000000
R/W 0x0
R/W Reset Value
R 0x0000000
R 0x0
R/W Reset Value
R 0x0
28-23