Samsung S3C6400X User Manual page 792

S3C6400X RISC MICROPROCESSOR
Protocol Register Matrix
As shown in Table 24-2 and Table 24-3, protocol registers are classed into 16 banks so that BSEL[3:0] must be
properly set before access.
MP_A[1:0]
Bank0
(0000)
00 CTRL
01 INTE
10 STAT
11
MP_A[1:0]
Bank8
(1000)
00 hDATAL
01 hDATAH
10 Reserved
11
SFR-mirrored registers: INTE, INTE1, STAT, STAT1, IMBH, IBML, OMBH, OMBL
Spare registers: BANK4_00, BANK4_01, BANK4_10, BANK5_00, BANK5_01, BANK5_10
Table 24-2 Protocol Register Matrix (Bank0 ~ Bank7)
Protocol Register (Selected by BSEL[3:0] )
Bank1 Bank2 Bank3
(0001) (0010) (0011)
CTRL1 IMBL OMBL
INTE1 IMBH OMBH
STAT1 reserved reserved
Table 24-3 Protocol Register Matrix (Bank8 ~ Bank15)
Protocol Register (Selected by BSEL[3:0] )
Bank9 Bank10
(1001) (1010)
Reserved Reserved
Reserved Reserved
Reserved Reserved
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Bank4
(0100)
Reserved Reserved
Reserved Reserved
Reserved Reserved
BSEL[3:0]
Bank11 Bank12
(1011) (1100)
SYS_CTRL Reserved
Reserved Reserved
Reserved Reserved
BSEL[3:0]
HOST INTERFACE
Bank5 Bank6
(0101) (0110)
Reserved
Reserved
Reserved
Bank13 Bank14
(1101) (1110)
Reserved Reserved
Reserved Reserved
Reserved Reserved
Bank7
(0111)
Reserved
Reserved
Reserved
Bank15
(1111)
Reserved
Reserved
Reserved
24-15