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S3C6400X RISC MICROPROCESSOR
N10 [3:0] : The number of EOF
pulse(0~15ea) before Vsync
asserts
N9 [2:0] : The location of the first P.S.
in format B
N9 [5:3] : The location of the first P.S.
in format A
Figure 17-12. Vertical Timing Diagram for pseudo sync and AGC pulse (macrovision control)
N10 [7:4] : The number of EOF pulse(0~15ea) after Vsync de-asserts
N14 [0:7] : on/off control of format B
N13 [0:7] : on/off control of format A
0
1
2
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
N12 [0:14] : AGC pulse type A / B (7~21 line)
N11 [0:14] : P.S and AGC on/off
3
4
5
6
7
TV ENCODER
(7~21 line)
N10 [2:0] : Interval of P.S.
in format B
N10 [5:3] : Interval of P.S.
in format A
N8 [2:0] : Period of P.S.
in format B
N8 [5:3] : Period of P.S.
in format A
17-13
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