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POST PROCESSOR
Y
1 Frame
Cb
Cr
Memory Space
(a) Non-Interleaving
31
Case E
Preliminary product information describe products that are in development,
15-6
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
WORD
MSB
LSB
Y Y
Y Y
Cb Cb
Cb Cb
Cr Cr
Cr Cr
Figure 15-3 Data format stored in external
Case A
Y/Cb/Cr
N+3
Case B
Y
N+1
Case B'
Y
N+1
Case C
Cb
N
Case C'
Cr
N
Case D
Don't Care
27 26
21 20
R[4:0]
G[5:0]
Pixel N+1
Figure 15-4 Byte and half-word organization Block Diagram
A
Video Data
1 Frame
Memory Space
Y/Cb/Cr
Y/Cb/Cr
N+2
N+1
Cb
Y
N
N
Cr
Y
N
N
Y
Cr
N+1
N
Y
Cb
N+1
N
R
G
N
N
16 15
11 10
B[4:0]
R[4:0]
S3C6400X RISC MICROPROCESSOR
WORD
MSB
Y Cb
Cb Y
Or
x
R
Pixel
N+1
(b) Interleaving
Y/Cb/Cr
N
Cr
N
Cb
N
Y
N
Y
N
B
N
5 4
0
G[5:0]
B[4:0]
Pixel N
LSB
B
Y Cr
Cr Y
C
G B
D
Pixel
E
N
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