Samsung S3C6400X User Manual page 324

S3C6400X RISC MICROPROCESSOR
12
VECTORED INTERRUPT CONTROLLER
This chapter describes the functions and usage of Vectored Interrupt Controller in S3C6400X RISC
microprocessor.
OVERVIEW
The interrupt controller in the S3C6400X is composed of 2 VIC's (Vectored Interrupt Controller, ARM PrimeCell
PL192) and 2 TZIC's (TrustZone Interrupt Controller, SP890).
Two TZIC's and VIC's are daisy-chained to support up to 64 interrupt sources. The TZIC provides a software
interface to the secure interrupt system in a TrustZone design. It provides secure control of the nFIQ interrupt and
masks the interrupt source(s) from the interrupt controller on the non-secure side of the system (VIC). You can
then use the latter to generate the nIRQ signal.
To generate nFIQ from the non-secure interrupt sources, the TZIC0 takes the nNSFIQIN signal from the
non-secure interrupt controller.
FEATURES
The Vectored Interrupt Controller features in S3C6400 incudes the following:
- Support for 32 vectored IRQ interrupts per VIC
- Fixed hardware interrupt priority levels
- Programmable interrupt priority levels
- Hardware interrupt priority level masking
- Programmable interrupt priority level masking
- IRQ and FIQ generation
- Software interrupt generation
- Test registers
- Raw interrupt status
- Interrupt request status
- Privileged mode support for restricted access
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
VECTORED INTERRUPT CONTROLLER
12-1