Samsung S3C6400X User Manual page 859

USB2.0 HS OTG
DEVICE OUT ENDPOINT COMMON INTERRUPT MASK REGISTER (DOEPMSK)
This register works with each of the Device OUT Endpoint Interrupt registers for all endpoints to generate an
interrupt per OUT endpoint. The OUT endpoint interrupts for a specific status in the DOEPINTn register can be
masked by writing to the corresponding bit in this register. Status bits are masked by default.
· Mask interrupt : 1'b0
· Unmask interrupt : 1'b1
Register Address
DOEPMSK 0x7C00_0814
DOEPMSK
Back2BackSETup
OUTTknEPdisMsk
SetUPMsk
AHBErrMsk
EPDisbldMsk
XferComplMsk
DEVICE ALL ENDPOINTS INTERRUPT REGISTER (DAINT)
When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register interrupts the application
using the Device OUT Endpoints Interrupt bit or Device IN Endpoints Interrupt bit of the Core Interrupt register.
There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN
endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register
are set and cleared when the application sets and clears bits in the corresponding Device Endpoint – n Interrupt
register.
Register Address
DAINT 0x7C00_0818
DAINT
OutEPInt [31:16]
InEpInt
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-52
Specifications and information herein are subject to change without notice.
R/W
R/W Device OUT Endpoint Common Interrupt Mask
Bit R/W
[31:7] Reserved
[6] R_W Back-to-Back SETUP Packets Received Mask
Applies to control OUT endpoints only.
[5] Reserved
[4] R_W OUT Token Received When Endpoint Disabled
Applies to control OUT endpoints only.
[3] R_W SETUP Phase Done Mask
Applies to control endpoints only.
[2] R_W AHB Error
[1] R_W Endpoint Disabled Interrupt Mask
[0] R_W Transfer Completed Interrupt Mask
R/W
R
Bit R/W
RO OUT Endpoint Interrupt Bits
One bit per OUT endpoint :
Bit 16 for OUT endpoint 0, bit 31 for OUT endpoint
15
[15:0] RO IN Endpoint Interrupt Bits
One bit per IN endpoint :
Description
Description
Description
Device ALL Endpoints Interrupt Register
Description
S3C6400X RISC MICROPROCESSOR
Reset Value
Initial State
Reset Value
Initial State
32 bits
27'h0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
32 bits
16'h0
16'h0