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MIPI HSI
FEATURES
THE MIPI HSI RX/TX CONTROLLER FEATURES:
The MIPI HSI interface is a uni-direction interface.
MIPI HSI Rx maximum bandwidth is 100Mbps. MIPI HSI TX controller uses PCLK for data transmitting.
Tx module:
Status register
FIFO status (fifo full, fifo empty, fifo write point, fifo read point)
MIPI status (internal status : current status & next status)
Configuration register
Operation mode select (stream mode or frame mode)
Fixed channel ID mode
Number of channel
Generated Error clear
TxHOLD state timer & enable
TxIDLE state timer & enable
TxREQ state timer & enable
Interrupt source register
FIFO empty
Break frame transfer done
TxHOLD state timeout
TxIDLE state timeout
TxREQ state timeout
Interrupt mask register
Software reset register
Channel ID register
Data register
Tx FIFO input
Tx FIFO size (Flip-Flop FIFO, not memory)
32bit width X 32 depth (128Byte)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
28-2
Specifications and information herein are subject to change without notice.
S3C6400X RISC MICROPROCESSOR
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