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S3C6400X RISC MICROPROCESSOR
Others control register
REGISTER
OTHERS
OTHERS
RESERVED
USB_SIG_MASK
USB_STATE
RESERVED
CLEAR_DBGACK
CLEAR_BATF_INT
RESERVED
SYNCMUXSEL
RESEVED
SPNIDEN
SPIDEN
CP15DISABLE
ADDRESS
R/W
0x7E00_F900
R/W
BIT
[31:17] RESERVED
USB signal mask to prevent unwanted leakage.
[16]
(This bit must set before USB PHY is used.)
USB PHY power state, read only bit (1: NORMAL, 0:
[15]
Power down)
[14]
DO NOT CHANGE
Clear DBGACK signal when this field has 1. ARM1176
asserts DBGACK signal to indicate the system has
[13]
entered Debug state. If DBGACK is asserted, this state
is store in SYSCON until software clear it using this
field.
Clear interrupt caused by battery fault when this bit is
[12]
set.
[11:7]
DO NOT CHANGE
[6]
SYNCMUX selection (0: MOUT
[5:3]
DO NOT CHANGE
Secure privileged non-invasive debug enable. This field
enables and disables non-invasive debug in the secure
world of ARM1176. If it is '1', non-invasive debug is
permitted in all non-secure mode. Otherwise, non-
[2]
invasive debug is not permitted in all secure secure
privileged mode. Non-invasive debug is permitted in
Secure use mode according to the SUNIDEN bit of
ARM1176.
Secure privileged invasive debug enable. This field
enables and disables invasive debug in the secure
world of ARM1176. If it is '1', invasive debug is
[1]
permitted in all secure mode. Otherwise, invasive
debus is not permitted in any secure privileged mode.
Invasive debug is permitted in Secure use mode
according to the SUNIDEN bit of ARM1176.
Disables write asses to some system control processor
[0]
registers of ARM1176. (0: enable, 1: disable)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
DESCRIPTION
Others control register
DESCRIPTION
, 1: DOUT
MPLL
SYSTEM CONTROLLER
RESET VALUE
0x0000_801E
RESET VALUE
0x0000
0
1
0
0
0
0x00
)
0
APLL
0x3
1
1
0
3-49
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