Samsung S3C6400X User Manual page 50

S3C6400X RISC MICROPROCESSOR
FIN
Fin / P
Pre-Divider
(P)
Fvco / M
P[5:0]
M[9:0]
P[5:0]
S[2:0]
PWRDN
Clock selection between PLL's and input reference clock
Figure 3-4 shows the clock generation logic. S3C6400X has three PLL's which are APLL for ARM operating clock,
MPLL for main operating clock, and EPLL for special purpose. The operating clocks are divided into three groups.
The first is ARM clock, which is generated from APLL. MPLL generates the main system clocks, which are used
for operating AXI, AHB, and APB bus operation. The last group is generated from EPLL. Mainly, the generated
clocks are used for peripheral IP's, i.e., UART, IIS, IIC, and etc.
AVDD10D AVSS10D
UP
Phase
Frequency
Detector
DN
M[9:0]
AVDD10A AVSS10A
Figure 3-3. PLL block diagram (APLL, MPLL only)
Figure 3-4. Clock generation from PLL outputs
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
AVBBD
Charge
Vctrl
Pump
C2
R1
C1
Main-Divider
(M)
AVBBA
SYSTEM CONTROLLER
DVSS10D
Voltage
Controlled
Oscillator
Scaler
(S)
Fvco
S[2:0]
FOUT
3-5