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MIPI HSI
INDIVIDUAL REGISTER DESCRIPTIONS (TX CONTROLLER)
STATUS_REG
STATUS_REG is an internal logic monitoring window.
Address = BASEADDR (0x7E00_6000)
Bits
Name
[31]
reserved
[30:28]
next_state
[27]
reserved
[26:24]
current state
[23:18]
reserved
[17]
FIFO_full
[16]
FIFO_empty
[15:13]
reserved
[12:8]
tx_rd_point
[7:5]
reserved
[4:0]
tx_wr_point
State register value
−
000 : IDLE
−
010 : Tx
−
100 : TxIDLE
−
110 : TxBRK
CONFIG_REG
CONFIG_REG is used to set the configuration of Tx controller.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
28-14
Specifications and information herein are subject to change without notice.
Description
Reserved bit
Next state*
Reserved bit
Current state*
Reserved bits
TxFIFO full
0 : FIFO not full
TxFIFO empty
0 : FIFO not empty
Reserved bits
TxFIFO read point
Reserved bits
TxFIFO write point
Table 28-6 STATUS_REG register description
001 : TxREQ
011 : TxHOLD
101 : Reserved state
111 : TxERR
S3C6400X RISC MICROPROCESSOR
R/W
R
R
R
R
R
R
1 : FIFO full
R
1 : FIFO empty
R
R
R
R
Reset Value
0x0
0x0
0x0
0x0
0x00
0x0
0x1
0x0
0x00
0x0
0x00
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