Samsung S3C6400X User Manual page 93

SYSTEM CONTROLLER
MTC_STABLE
RESERVED
DOMAIN_ETM
DOMAIN_S
DOMAIN_F
DOMAIN_P
DOMAIN_I
DOMAIN_V
DOMAIN_TOP
MTC_STABLE represents the number of external oscillator (or clock) cycles. When a sub-block returns from MTC
mode to normal operation mode, the internal power stabilization time is required. This period must be larger than
200nsec and it can be estimated using MTC_STABLE value and OSC_FREQ registers.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
3-48
Specifications and information herein are subject to change without notice.
BIT
[31:28] RESERVED
[27:24] Memory power stabilization counter for domain ETM
[23:20] Memory power stabilization counter for domain S
[19:16] Memory power stabilization counter for domain F
[15:12] Memory power stabilization counter for domain P
[11:8] Memory power stabilization counter for domain I
[7:4] Memory power stabilization counter for domain V
[3:0] Memory power stabilization counter for domain TOP
S3C6400X RISC MICROPROCESSOR
DESCRIPTION RESET VALUE
0xF
0xF
0xF
0xF
0xF
0xF
0xF
0xF