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S3C6400X RISC MICROPROCESSOR
START
Slave Tx mode has
been configured.
IIC detects start signal. and, IICDS
receives data.
IIC compares IICADD and IICDS (the
received slave address).
Matched?
Y
The IIC address match
interrupt is generated.
Write data to IICDS.
Clear pending bit to
resume.
Stop?
N
The data of the IICDS is
shifted to SDA.
Interrupt is pending.
Figure 30-7. Operations for Slave/Transmitter Mode
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
N
Y
END
IIC-BUS INTERFACE
30-9
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