Samsung S3C6400X User Manual page 133

S3C6400X RISC MICROPROCESSOR
SIGNAL DESCRIPTION
External Memory Interface
Signal
Xm0DATA
[15:0]
Xm0CSn[1:0]
Xm0WEn
Xm0OEn
Xm0INTsm0_FWEn
Xm0INTsm1_FREn
Xm0ADDRVALID
Xm0RPn
Xm0RDY0_ALE
Xm0RDY1_CLE
Xm0SMCLK
I/O
Xm0DATA[15:0] (Data Bus) outputs address during memory read/write address
IO phase, inputs data during memory read data phase and outputs data during
memory write data phase.
Xm0CSn[1:0] (Chip Select) are activated when the address of a memory is within
the address region of each bank. Xm0CSn[1:0] can be assigned to either SROMC
O
or OneNAND controller by System Controller SFR setting.
Active LOW.
Xm0WEn (Write Enable) indicates that the current bus cycle is a write cycle.
O
Active LOW.
Xm0OEn (Output Enable) indicates that the current bus cycle is a read cycle.
O
Active LOW.
Interrupt inputs from OneNAND memory Bank 0, 1.
I
If OneNAND memory is not used, these signals must be tied to zero.
Address valid output. In the POP products, address and data are multiplexed.
Xm0ADDRVALID indicate when the bus is used for address.
O
Active LOW.
System reset output for OneNAND memory.
O
Active LOW.
Xm0RDY is a synchronous burst wait input that the external device uses to delay a
I synchronous burst transfer. Xm0RDY indicates data valid in synchronous read
modes and is activated while Xm0CSn is low.
O Static memory clock for synchronous static memory devices.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
ONENAND CONTROLLER
Description
7-3