Samsung S3C6400X User Manual page 107

S3C6400X RISC MICROPROCESSOR
5
DRAM CONTROLLER
OVERVIEW
DRAM Controller is from ARM PrimeCell CP003 AXI Dynamic Memory Controller (PL340) based on ARM
PrimeCell CP003 AXI DMC (PL340). Original AMBA APB 3.0 port for programming configuration registers is
covered by using AxiToApb bridge component, which implements an AXI slave port connected to an APB master
port.
DRAM Controller has AMBA AXI compatible bus for programming its configuration registers and for access to
SDRAM. DRAM Controller can be programmed by writing chip configuration, ID configuration, and memory timing
parameters in PL340 configuration registers. The two lower bits in the user_config register are used to select
memory type.
DRAM Controller can receive a direct command for SDRAM or DRAM Controller itself. By writing command to
direct_cmd register, DRAM Controller can send commands like 'Prechargeall', 'Autorefresh', 'NOP', and 'MRS'
('EMRS') to SDRAM. By writing command to memc_cmd register, DRAM Controller can enter into states like
'Config', 'Ready', and 'Low_power'.
DRAM Controller supports power-down in three ways. The DRAM Controller can automatically place the SDRAM
into either the pre-charge power-down or active power-down
when the SDRAM has been inactive for a number of clock cycles set in memory_cfg. The DRAM controller can
place the SDRAM into the self-refresh state under software control by writing command in memc_cmd, or under
hardware control by using AXI low-power interface.
The auto-refresh command is issued to SDRAM periodically when refresh counter reaches the value of the
refresh period in auto-refresh period register.
FEATURES
Supports SDR SDRAM, mobile SDR SDRAM, DDR SDRAM, and mobile DDR SDRAM
Supports 2 external memory chips.
Supports 32/64-bit AMBA AXI bus.
Supports 16/32-bit memory bus.
Address space: up to 512MByte per port.
Supports asynchronous operation between AXI bus and external memory bus.
Provides active and pre-charge power down.
Quality of Service features for low latency transfers.
Optimized utilization of external memory bus.
Support to select external memory types by setting SFR.
Supports 8 outstanding addresses.
Supports data-write interleaving with depth 8.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
state, by de-asserting DMC0_CKE or DMC1_CKE
DRAM CONTROLLER
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