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S3C6400X RISC MICROPROCESSOR
INPUT
ARGUMENT
OUTPUT
BASE+0x1C0
RETURN
BASE+0x1C4
BASE+0x1C8
BASE+0x1CC
BASE+0x1D0
BASE+0x1D4
5
Bits for representing File Play mode, Dynamic Buffer Allocation enable are added to this register
6
From 18C to 1A0, this registers are added to provide a way to use work buffer configurable.
7
A bit for representing Annex-J indication is added to this register.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-54
Specifications and information herein are subject to change without notice.
Table 21.6. DEC_SEQ_INIT Parameter Register Summary
Address
Type
BASE+0x180
R/W
BASE+0x184
R/W
BASE+0x188
R/W
BASE+0x18C
R/W
BASE+0x190
R/W
BASE+0x194
R/W
BASE+0x198
R/W
BASE+0x19C
R/W
BASE+0x1A0
R/W
BASE+0x1A4
R/W
R
R
R
R
R
R
DEC_SEQ_INIT
Name
CMD_DEC_SEQ_BIT_BUF_START
CMD_DEC_SEQ_BIT_BUF_SIZE
CMD_DEC_SEQ_OPTION5
CMD_DEC_SEQ_PRO_BUF
CMD_DEC_SEQ_TMP_BUF_1
CMD_DEC_SEQ_TMP_BUF_2
CMD_DEC_SEQ_TMP_BUF_3
CMD_DEC_SEQ_TMP_BUF_4
CMD_DEC_SEQ_TMP_BUF_5
CMD_DEC_SEQ_START_BYTE
RET_DEC_SEQ_SUCCESS
RET_DEC_SEQ_SRC_SIZE
RET_DEC_SEQ_SRC_F_RATE
RET_DEC_SEQ_FRAME_NEED
RET_DEC_SEQ_FRAME_DELAY
7
RET_DEC_SEQ_INFO
MULTI-FORMAT VIDEO CODEC
Description
Bitstream Buffer Address
Bitstream Buffer Size
Decoding sequence option
Process Buffer Address
Temporary Buffer1 Address
Temporary Buffer2 Address
Temporary Buffer3 Address
Temporary Buffer4 Address
Temporary Buffer5 Address6
Start byte of valid stream data
Command executing result
status
Decoded source picture size
Decoded source frame rate
Required minimum decoded
frame buffer
Maximum display frame buffer
delay
Decoded sequence
information
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