Samsung S3C6400X User Manual page 827

USB2.0 HS OTG
DbnceDone
ADevTOUTChg
HstNegDet
[16:10]
HstnegSucStsChn
g
SesReqSucStsCh
ng
SesEndDet
OTG AHB CONFIGURATION REGISTER (GAHBCFG)
This register can be used to configure the core after power-on or a change in mode of operation. This register
mainly contains AHB system-related configuration parameters. Do not change this register after the initial
programming. The application must program this register before starting any transactions on either the AHB or the
USB.
Register Address
GAHBCFG 0x7C00_0008
GAHBCFG
PTxFEmpLvl
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-20
Specifications and information herein are subject to change without notice.
[19] R_SS_ Debounce Done
WC
The core sets this bit when the debounce is
completed after the device connects. This bit is only
valid when the HNP Capable or SRP Capable bit is
set in the Core USB Configuration register.
[18] R_SS_ A-Device Timeout Change
WC
The core sets this bit to indicate that the A-device
has timed out while waiting for the B-device to
connect.
[17] R_SS_ Host Negotiation Detected
WC
The core sets this bit when it detects a host
negotiation request on the USB.
Reserved
[9] R_SS_ Host Negotiation Success Status Change
WC
The core sets this bit on the success or failure of a
USB host negotiation request.
[8] R_SS_ Session Request Success Status Change
WC
The core sets this bit on the success or failure of a
session request.
[7:3] Reserved
[2] R_SS_ Session End Detected
WC
The core sets this bit when the b_valid signal is
deasserted.
[1:0] Reserved
R/W
R/W
Bit R/W
[31:9] Reserved
[8] R_W Periodic TxFIFO Empty Level
Indicates when the Periodic TxFIFO Empty Interrupt
bit in the Core Interrupt register
(GINTSTS.PTxFEmp) is triggered. This bit is used
only in Slave mode.
· 1'b0 : GINTSTS.PTxFEmp interrupt indicates that
Description
Core AHB Configuration Register
Description
S3C6400X RISC MICROPROCESSOR
Reset Value
Initial State
1'b0
1'b0
1'b0
7'h0
1'b0
1'b0
5'h0
1'b0
2'h0
32 bits
23'h0
1'b0