Samsung S3C6400X User Manual page 875

USB2.0 HS OTG
DIEPDMAn/
DOEPDMAn
DMAAddr
POWER AND CLOCK GATING CONTROL REGISTER (PCGCCTL)
The application can use this register to control OTG's clock gating.
Register Address
PCGCCTL 0x7C00_0E00
DIEPTSIZ0
StopPclk
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-68
Specifications and information herein are subject to change without notice.
Bit R/W
[31:0] R_W DMA Address
Holds the start address of the external memory for
storing or fetching endpoint data. This register is
incremented on every AHB transaction.
Note: For control endpoints, this address stores
control OUT data packets as well as SETUP
transaction data packets. If multiple SETUP packets
are received back-to-back, the SETUP data packet
in the memory is overwritten.
R/W
R/W
Bit R/W
[31:1] Reserved
[0] R_W STOP Pclk
The application sets this bit to stop the PHY clock
when the USB is suspended, the session is not valid,
or the device is disconnected. The application clears
this bit when the USB is resumed or a new session
starts.
Description
Description
Power and Clock Gating Control Register
Description
S3C6400X RISC MICROPROCESSOR
Initial State
Reset Value
Initial State
32'h0
32 bits
31'h0
1'b0