Samsung S3C6400X User Manual page 854

S3C6400X RISC MICROPROCESSOR
DEVICE MODE REGISTERS
These registers are visible only in Device mode and must not be accessed in Host mode, as the results are
unknown. Some of them affect all the endpoints uniformly, while others affect only a specific endpoint. Device
Mode registers fall into two categories:
· Device Global registers
· Device logical endpoint-specific registers
DEVICE GLOBAL REGISTERS
DEVICE CONFIGURATION REGISTER (DCFG)
This register configures the core after power-on or after certain control commands or enumeration. Do not make
changes to this register after initial programming.
Register Address
DCFG 0x7C00_0800
DCFG
[31:23]
EPMisCnt [22:18]
[17:13]
PerFrInt [12:11]
DevAddr
NZStsOUTHShk
R/W
R/W
Bit R/W
Reserved
R_W IN Endpoint Mismatch Count
The application programs this field with a count that
determines when the core generates an Endpoint
Mismatch interrupt. The core loads this value into an
internal counter and decrements it. The counter is
reloaded whenever there is a match or when the
counter expires. The width of this counter depends
on the depth of the Token Queue.
Reserved
R_W Periodic Frame Interval
Indicates the time within a (micro)frame at which the
application must be notified using the End Of
Periodic Frame Interrupt. This can be used to
determine if all the isochronous traffic for that
(micro)frame is complete.
· 2'b00 : 80% of the (micro)frame interval
· 2'b01 : 85%
· 2'b10 : 90%
· 2'b11 : 95%
[10:4] R_W Device Address
The application must program this field after every
SetAddress control command.
[3] Reserved
[2] R_W Non-Zero-Length Status OUT Handshake
The application can use this field to select the
handshake the core sends on receiving a nonzero-
length data packet during the OUT transaction of a
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Device Configuration Register
Description
USB2.0 HS OTG
Reset Value
32 bits
Initial State
9'h0
5'h8
5'h0
2'h0
7'h0
1'b0
1'b0
26-47