Samsung S3C6400X User Manual page 931

S3C6400X RISC MICROPROCESSOR
ERROR INTERRUPT STATUS ENABLE REGISTER
Setting to 1 enables Error Interrupt Status.
Register
ERRINTSTSEN0 0x7C200036
ERRINTSTSEN1 0x7C300036
ERRINTSTSEN2 0x7C400036
Name Bit
[15:9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Address R/W
R/W
R/W
R/W
Reserved
Auto CMD12 Error Status Enable
'1' = Enabled
'0' = Masked
Current Limit Error Status Enable
This function is not implemented in this version.
'1' = Enabled
'0' = Masked
Data End Bit Error Status Enable
'1' = Enabled
'0' = Masked
Data CRC Error Status Enable
'1' = Enabled
'0' = Masked
Data Timeout Error Status Enable
'1' = Enabled
'0' = Masked
Command Index Error Status Enable
'1' = Enabled
'0' = Masked
Command End Bit Error Status Enable
'1' = Enabled
'0' = Masked
Command CRC Error Status Enable
'1' = Enabled
'0' = Masked
Command Timeout Error Status Enable
'1' = Enabled
'0' = Masked
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Error Interrupt Status Enable Register
(Channel 0)
Error Interrupt Status Enable Register
(Channel 1)
Error Interrupt Status Enable Register
(Channel 2)
Description
HSMMC CONTROLLER
Reset Value
0x0
0x0
0x0
Initial Value
0
0
0
0
0
0
0
0
0
0
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