Samsung S3C6400X User Manual page 870

S3C6400X RISC MICROPROCESSOR
DEVICE ENDPOINT-n INTERRUPT REGISTER (DIEPINTn/DOEPINTn)
Endpoint_number : 0≤ n≤ 15
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The application
must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt
register is set. Before the application can read this register, it must first read the Device All Endpoints Interrupt
(DAINT) register to get the exact endpoint number for the Device Endpoint-n Interrupt register. The application
must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
Register Address
DIEPINTn 0x7C00_0908
+n*20h /
/
0x7C00_0B08
DOEPINTn
+n*20h
DIEPINTn/
DOEPINTn
EPEna
INEPNakEff
Back2BackSETup
INTknEPMis
R/W
R/W
Bit R/W
[31:7] Reserved
[6] RO IN Endpoint NAK Effective
Applies to periodic IN endpoints only.
Indicates that the IN endpoint NAK bit set by the
application has taken effect in the core. This bit can
be cleared when the application clears the IN
endpoint NAK by writing to DIEPCTLn.CNAK.
This interrupt indicates that the core has sampled
the NAK bit set.
This interrupt does not necessarily mean that a NAK
handshake is sent on the USB. A STALL bit takes
priority over a NAK bit.
Back-to-Back SETUP Packets Received
Applies to Control OUT endpoints only.
R_W
This bit indicates that core has received more than
three back-to-back SETUP packets for this particular
endpoint.
[5] R_SS_ IN Token Received with EP Mismatch
WC Applies to periodic IN endpoints only.
Indicates that the data in the top of the non-periodic
TxFIFO belongs to an endpoint other than the one
for which the IN token was received. This interrupt is
asserted on the endpoint for which the IN token was
received.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Device Endpoint-n Interrupt Register
Description
USB2.0 HS OTG
Reset Value
32 bits
Initial State
25'h0
1'b0
1'b0
26-63