Samsung S3C6400X User Manual page 796

S3C6400X RISC MICROPROCESSOR
In-Mail Box Low Register (IMBL)
BSEL[3:0] = 0010, MP_A[1:0] = 00, R/W, Reset value = 0x0000
Field
IMBL
In-Mail Box High Register (IMBH)
BSEL[3:0] = 0010, MP_A[1:0] = 01, R/W, Reset value = 0x0000
Field
IMBH
Out-Mail Box Low Register (OMBL)
BSEL[3:0] = 0011, MP_A[1:0] = 00, R, Reset value = 0x0000
Field
OMBL
Out-Mail Box High Register (OMBH)
BSEL[3:0] = 0011, MP_A[1:0] = 01, R, Reset value = 0x0000
Field
OMBH
Bit
[15:0] Lower 16 bits of In-Mail Box register
CPU writes a 16-bit data into IMBL.
Bit
[15:0] Upper 16 bits of In-Mail Box register
After CPU writes a 16-bit data into IMBH, CPUIF Client asserts
'IMB_flag' (an internal signal) in order to notify that a 32-bit IMB
contains a new value. IMB_flag is automatically cleared when
IMB is read by software.
Bit
[15:0] Lower 16 bits of Out-Mail Box register
CPU reads a lower 16-bit data of a 32-bit OMB.
Bit
[15:0] Upper 16 bits of Out-Mail Box register
When the host reads an upper 16-bit data of a 32-bit OMB,
STAT1[0] (ie, OMB flag) is automatically cleared.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
Description
Description
HOST INTERFACE
Initial State
0x0000
Initial State
0x0000
Initial State
0x0000
Initial State
0x0000
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