Samsung S3C6400X User Manual page 53

SYSTEM CONTROLLER
OneNAND clock generation
Figure 3-7 shows clock generators for OneNAND interface controller. OneNAND interface controller requires
additional synchronized clock which must be half of the other clock frequency. As shown in the Figure 3-7, the
clock is generated from HCLK.
MFC clock generation
The MFC block requires a special clock in addition to HCLK and PCLK. The additional clock is generated as
shown in Figure 3-8.
The source clock is selected between HCLKX2 and MOUT
operating frequency of HCLKX2 is fixed as 266MHz by default. Therefore, CLK_DIV0 [31:28] must be 4'b0001 to
generate 133MHz. When MFC is not required full-performance, there are two way to decrease the operating
frequency. The first is to use output clock of EPLL when CLK_SRC [4] is set 1. Generally, EPLL is used for audio
clocks and the output clock will be lower than output frequency of MPLL. Another way is to adjust clock divider
ratio of CLK_DIV0 [31:28]. Using this value, the lower frequency can be applied to MFC block using CLK_SRC [4]
field to reduce redundant power dissipation. Since the output frequency of EPLL is independent of HCLKX2 or
HCLK.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
3-8
Specifications and information herein are subject to change without notice.
Figure 3-7. OneNAND clock generation
Figure 3-8. MFC clock generation
EPLL
S3C6400X RISC MICROPROCESSOR
. The operating clock is divided using HCLKX2. The