S3C6400X RISC MICROPROCESSOR
INDIVIDUAL REGISTER DESCRIPTIONS (RX CONTROLLER)
STATUS_REG
STATUS_REG is an internal logic monitoring window.
Address = BASEADDR
Bits
Name
[31]
Reserved
[30:28]
Next_state
[27]
Reserved
[26:24]
Curr_state
[23:19]
Reserved
[18]
FIFO_timeout
[17]
FIFO_full
[16]
FIFO_empty
[15:14]
Reserved
[13:8]
Rx_rd_point
[7:6]
Reserved
[5:0]
Rx_wr_point
State register value
−
000 : IDLE
−
010 : Rx
−
100 : RxBREAK
−
110 : RxRST
Description
Reserved bit
Next state*
Reserved bit
Current state*
Reserved bits
RxFIFO read timeout
0 : in time
RxFIFO full
0 : FIFO not full
RxFIFO empty
0 : FIFO not empty
Reserved bits
RxFIFO read point
Reserved bits
RxFIFO write point
Table 28-13 STATUS_REG register description
001 : RxACK
011 : RxHOLD
101 : Reserved state
111 : RxERR
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1 : time out
1: FIFO full
1: FIFO empty
MIPI HSI
R/W
Reset Value
R
0x0
R
0x0
R
0x0
R
0x0
R
0x00
R
0x0
R
0x0
R
0x1
R
0x0
R
0x00
R
0x0
R
0x00
28-19