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S3C6400X RISC MICROPROCESSOR
ADDR_EXPAND
ENDIAN
MP0_CS_SEL
[5:0]
SROMC - DMC0 - OneNANDC CS0 - OneNANDC CS1 –
5
NFCON – CFCON
Set usage of Xm1DATA[31:16] pins.
0 = Xm1DATA[31:16] pins are used for DMC1 upper halfword
[7]
data field, data[31:16].
1 = Xm1DATA[31:16] pins are used for SROMC upper 10-bit
address field, address[25:16].
Set endian control for SROMC, NFCON, and internal ROM.
[6]
0 = Little-endian memory system.
1 = Big-endian byte-invariant memory system.
Set static memory chip selection multiplexing of memory port
0.
Setting for MP0_CS_SEL[0] and MP0_CS_SEL[2] are
ignored. Distinguishing OneNANDC and NFCON is done by
XSELNAND pin value instead of MP0_CS_SEL[0] and
MP0_CS_SEL[2]. When XSELNAND is 0, OneNANDC is
selected. When XSELNAND is 1, NFCON is selected.
When NAND booting (OM[4:3] = 00) is selected, the setting
values of MP0_CS_SEL[1] and MP0_CS_SEL[3] as well as
XSELNAND setting are ignored and Xm0CSn[2] and
Xm0CSn[3] are used as NFCON CS0 and NFCON CS1. In
this case, XSELNAND should be set to 1.
When OneNAND booting (OM[4:1] = 0110) is selected, the
setting values of MP0_CS_SEL[1] and MP0_CS_SEL[3] are
ignored and Xm0CSn[2] and Xm0CSn[3] are used as
OneNANDC CS0 and OneNANDC CS1. In this case,
XSELNAND should be set to 0.
Xm0CSn[0]
Xm0CSn[1]
Xm0CSn[2]
Xm0CSn[3]
Xm0CSn[4]
Xm0CSn[5]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
MP0_CS_SEL
[5] [4] [3] [2] [1] [0]
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1
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0
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0
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1
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0
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0
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0
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1
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0
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1
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SYSTEM CONTROLLER
SROMC CS0
SROMC CS1
SROMC CS2
OneNANDC CS0
NFCON CS0
SROMC CS3
OneNANDC CS1
NFCON CS1
SROMC CS4
CFCON CS0
SROMC CS5
CFCON CS1
1
0
0x00
3-41
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