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FIMV-MFC V1.0
MULTI-FORMAT
CODEC
VIDEO
Macroblock Controller
FIMV-MFC V1.0 has a complex and large number of pipeline for high-performance. To manage it wholly by the
BIT processor is not suitable. Therefore, FIMV-MFC V1.0 embeds the macroblock controller to control all sub
module of the video codec based on the configuration of pipelining by the BIT processor. This scheme reduces
the load on the BIT processor and guarantees the programmability of the IP.
Before the video codec encode or decode a macroblock, the BIT processor configures how the pipeline of the
codec is structured. If all processes are completed for encoding/decoding a macroblock, the macroblock controller
indicates its completion.
To summarize, the BIT processor configures which sub-modules are enabled for current macroblock processing,
and the macroblock controller manages corresponding sub-modules based on the configuration.
Figure 21.40. Macroblock controller connectivity
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-49
Specifications and information herein are subject to change without notice.
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