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IIC-BUS INTERFACE
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
30-8
Specifications and information herein are subject to change without notice.
START
Master Rx mode has
been configured.
Write slave address to
IICDS.
Write 0xB0 (M/R
Start) to IICSTAT.
The data of the IICDS (slave
address) is transmitted.
ACK period and then
interrupt is pending.
Stop?
N
Read a new data from
IICDS.
Clear pending bit to
resume.
SDA is shifted to IICDS.
Figure 30-6. Operations for Master/Receiver Mode
S3C6400X RISC MICROPROCESSOR
Y
Write 0x90 (M/R
Stop) to IICSTAT.
Clear pending bit .
Wait until the stop
condition takes effect.
END
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