Samsung S3C6400X User Manual page 855

USB2.0 HS OTG
DevSpd
DEVICE CONTROL REGISTER (DCTL)
Register Address
DCTL 0x7C00_0804
DCTL
[31:12]
PWROnPrgDone
CGOUTNak
SGOUTNak
CGNPInNAK
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-48
Specifications and information herein are subject to change without notice.
control transfer's Status stage.
· 1'b0 : Send a STALL handshake on a nonzero-
length status OUT transaction and do not send the
received OUT packet to the application.
· 1'b1 : Send the received OUT packet to the
application and send a handshake based on the
NAK and STALL bits for the endpoint in the Device
Endpoint Control register.
[1:0] R_W Device Speed
Indicates the speed at which the application requires
the core to enumerate, or the maximum speed the
application can support. However the actual bus
speed is determined only after the chirp sequence is
completed, and is based on the speed of the USB
host to which the core is connected.
· 2'b00 : High speed (USB 2.0 PHY clock is 30 Mhz
or 60 Mhz)
· 2'b01 : Full speed (USB 2.0 PHY clock is 30 Mhz
or 60 Mhz)
· 2'b10 : Low speed (USB 1.1 transceiver clock is 6
Mhz). If you select 6 MHz LS mode, you must do a
soft reset.
· 2'b11 : Full speed (USB 1.1 transceiver clock is 48
Mhz).
R/W
R/W
Bit R/W
Reserved
[11] R_W Power-On Programming Done
The application uses this bit to indicate that register
programming is completed after a wake-up from
Power Down mode.
[10] WO Clear Global OUT NAK
A write to this field clears the Global OUT NAK.
[9] WO Set Global OUT NAK
A write to this field sets the Global OUT NAK.
The application uses this bit to send a NAK
handshake on all OUT endpoints.
The application must set the his bit only after making
sure that the Global OUT NAK Effective bit in the
Core Interrupt Register is cleared.
[8] WO Clear Global Non-Periodic IN NAK
A write to this field clears the Global Non-Periodic IN
S3C6400X RISC MICROPROCESSOR
Description
Device Control Register
Description
2'b0
Reset Value
32 bits
Initial State
20'h0
1'b0
1'b0
1'b0
1'b0