Samsung S3C6400X User Manual page 428

DISPLAY CONTROLLER
LCD_WR_ACT
LCD_WR _HOLD
-
RSPOL
-
I80IFEN
LCD I80 Interface Control 1
Register Address
I80IFCONB0 0x771001B8
I80IFCONB1 0x771001BC
I80IFCONBx
-
NORMAL_CMD_ST
-
FRAME_SKIP
-
AUTO_CMD_RATE
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
14-66
Specifications and information herein are subject to change without notice.
[11:8] Numbers of clock cycles for the active period of the chip
select enable.
[7:4] Numbers of clock cycles for the active period of the chip
select disable to the write signal disable.
[3] Reserved
[2] The polarity of the RS Signal
0: RS signal is low during video data transfer.
1: RS signal is high during video data transfer.
[1] Reserved
[0] LCD I80 Interface control
0: Disable
1: Enable
R/W
R/W I80 Interface control for Main LDI(LCD)
R/W I80 Interface control for Sub LDI(LCD)
Bit
Reserved
[11:10]
[9] 1 : Normal Command Start
* Auto clear after sending one set of commands
Reserved
[8:7]
[6:5] I80 Interface Output Frame Decimation Factor
00 : 1 (No Skip)
01 : 2
10 : 3
Reserved
[4]
0000 : Disable auto command
[3:0]
0001 : per 2 Frames
0010 : per 4 Frames
0011 : per 6 Frames
S3C6400X RISC MICROPROCESSOR
Description
Description
0
0
0
0
0
Reset Value
0x0
0x0
Initial State
0
0
00
0
0000