Samsung S3C6400X User Manual page 823

USB2.0 HS OTG
OTG PHY CLOCK CONTROL REGISTER (OPHYCLK)
Register Address
OPHYCLK 0x7C10_0004
OPHYCLK
serial_mode
xo_ext_clk_enb
common_on_n
xo_on_n
id_pullup
clk_sel
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-16
Specifications and information herein are subject to change without notice.
R/W
R/W
Bit R/W
[31:7] Reserved
[6] R_W UTMI/Serial Interface Select
When this register is asserted, USB traffic flows
through the serial interface.
· 1'b0: Data on the D+ and D- lines is transmitted
and received through the UTMI.
· 1'b1: Data on the D+ and D- lines is transmitted
and received through the USB1.1 Serial Interface.
[5] R_W Reference Clock Select for XO Block
· 1'b0: external crystal
· 1'b1: external clock/oscillator
[4] R_W Force XO, Bias, Bandgap, and PLL to Remain
Powered During a Suspend
This bit controls the power-down signals of sub-
blocks in the Common block when the USB 2.0 OTG
PHY is suspended.
· 1'b0 : 48MHz clock on clk48m_ohci is available at
all times, except in Suspend mode.
· 1'b1 : 48MHz clock on clk48m_ohci is available at
all times, even in Suspend mode.
[3] R_W Force XO Block On During a Suspend
· 1'b0 : If all ports are suspended, the XO block is
powered up, and the clk_ref_ohci(48MHz clock
source for other IPs) signal is available.
· 1'b1 : XO block is powered down when all ports are
suspended.
[2] R_W Analog ID Input Sample Enable
· 1'b0 : id_dig disable.
· 1'b1 : id_dig enable. (The id_dig output is valid, and
within 20ms, id_dig must indicate which type of plug
is connected.)
[1:0] R_W Reference Clock Frequency Select for PLL
· 2'b00 : 48MHz
· 2'b01 : Reserved
· 2'b10 : 12MHz
· 2'b11 : 24MHz
S3C6400X RISC MICROPROCESSOR
Description
OTG PHY Control Register
Description
Reset Value
32 bits
Initial State
25'h0
1'b0
1'b0
1'b0
1'b0
1'b0
2'b00