Samsung S3C6400X User Manual page 569

CAMERA INTERFACE
TIMING DIAGRAM
VSYNC
HREF
HREF (1H)
PCLK
DATA[7:0]
PCLK
DATA[7:0]
There are two timing reference signals in ITU-R BT 656 format, one at the beginning of each video data block
(start of active video, SAV) and one at the end of each video data block(end of active video, EAV) as shown in
Figure 20-3 and Table 20-3.
Data bit number
7 (MSB)
6
5
4
3
2
Preliminary product information describe products that are in development,
20-4
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Y Cb Y Cr
Figure 20-2. ITU-R BT 601 Input timing diagram
FF 00 00 XY
Video timing
reference codes
Figure 20-3. ITU-R BT 656 Input timing diagram
First word Second word
1
1
1
1
1
1
1 frame
Vertical lines
Horizontal width
8- bit mode
Y Cb Y
Y Cb Cr
Pixel data
Third word
0
0
0
0
0
0
S3C6400X RISC MICROPROCESSOR
Cb Y Cr
FF 00 00 XY
Video timing
reference codes
Fourth word
0
0 F
0 V
0 H
0 P3
0 P2
1