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MIPI HSI
Address = BASEADDR + 0x1C
Bits
Name
[31:0]
TxFIFO in
Note: If willing to transfer data is loaded on TxFIFO, data which is located on FIFO is transferred to the other
side's RX through MIPI HSI Tx controller until TxFIFO is fully empty.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
28-18
Specifications and information herein are subject to change without notice.
Description
TxFIFO data input for transmitting
Table 28-12 DATA_REG register description
S3C6400X RISC MICROPROCESSOR
R/W
Reset Value
W
0x0
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