Samsung S3C6400X User Manual page 777

MODEM INTERFACE
MSM Interrupt Clear Register (MSMINTCLR)
Register
MSMINTCLR 0x74108010
MSMINTCLR Bit
- [31:0]
Note. The interrupt controllers of AP(S3C6400X), VIC, receive level-triggered type interrupt requests. Therefore,
interrupt requests from MODEM_IF block are maintained until ARM(the interrupt service routine S/W) clears this
register by writing to HIGH.
23-12
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Ohters : XhiADDR[8] -> bypass_RS
Address R/W
W
Write access to this register with any data will clear the interrupt
pending register of MSM modem interface.
Description
MSM Modem Interface Pending Interrupt
Request Clear
Description
S3C6400X
RISC MICROPROCESSOR
Reset Value
-
-
Initial State