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S3C6400X RISC MICROPROCESSOR
Detailed Description of BIT Processor Registers
CodeRun (0x000)
Bit
0
CodeDownLoad (0x004)
Bit
15:0
28:16
HostIntReq (0x008)
Bit
0
BitIntClear (0x00C)
Bit
0
BitIntSts (0x010)
Bit
0
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-60
Specifications and information herein are subject to change without notice.
Name
Type
CodeRun
W
0 – BIT Processor stop execution
1 – BIT Processor start execution
Name
Type
CodeData
W
16 bit BIT code download data
CodeAddr
W
13 bit BIT code download address
BIT code word address (16 bit address)
* Current design has 4 K code word space (8 KB).
Therefore CodeAddr[12:0] must be less than 4095
Name
Type
IntReq
W
Interrupt request to BIT processor.
Host can write '1' to this register to request interrupt
to BIT
* Current firmware version does not use Interrupt
from Host to BIT. Therefore this register is not used
Name
Type
IntClear
W
Writing '1' to this register clear BIT interrupt to host
Name
Type
IntSts
R
1 means that BIT interrupts to host is asserted.
This bit is cleared when Host writes IntClear Register
'1'
MULTI-FORMAT VIDEO CODEC
Function
Function
Function
Function
Function
Reset Value
0
Reset Value
0
0
Reset Value
0
Reset Value
0
Reset Value
0
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